Job Description

Job Responsibilities:

• Perform physical layout and verification of integrated circuit building blocks
• Perform full-chip assembly and top-level verification
• Apply best practices for managing local process variation through layout techniques
• Apply high-speed digital and RF layout techniques to minimize unwanted parasitic interactions
• Collaborate with a multi-person design team to support effective implementation and verification of circuit designs
• Support design activities through multiple stages of the integrated circuit development and tape-out process

Skills:

• Deep-Submicron CMOS Layout
• Cadence IC Design Flow
• DRC, LVS, and Parasitic Extraction
• Calibre and Assura
• Top-Level Floor Planning
• Block-Level IC Design
• Analog/Mixed-Signal Layout
• Integrated Circuit Design and Tape-Out

Education/Experience:

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related technical field — Preferred

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